The motivation for this project is NTP servers in datacenters - it can be expensive to get a GPS antenna on top of other people's buildings with a wire running down into your rack. The question is, how do you maximize the accuracy of a stratum 2 NTP server? The
History I'm bringing my RTC Hats [https://blog.dan.drown.org/tag/stratum2/] back online (source code [https://github.com/ddrown/stm32-input-capture-f031] and hardware design [https://github.com/ddrown/stm32-input-capture-f031/tree/master/hardware] is on github). I originally designed it for frequency synchronization without phase alignment [https://blog.dan.drown.
I'll test what happens when I plug my embedded NTP client directly into my NTP servers, bypassing the Ethernet switch. This ends my long running embedded NTP client series. The systems involved Embedded NTP client (Archmax): Part 4 [https://blog.dan.drown.org/embedded-ntp-client-ntp-interleaved-mode-part-4/], Part 3 [https://blog.dan.drown.
Part 3 [https://blog.dan.drown.org/embedded-ntp-client-ntp-interleaved-mode-part-3/] ended with an unexplained 3us offset, this post will reduce that. Verifying PTP clock sync I wanted to measure the NTP client's PTP clock sync externally. The PTP peripheral has the option to output a PPS that I can compare to the
Previous posts: part 1 [https://blog.dan.drown.org/archmax-ntp-client/], part 2 [https://blog.dan.drown.org/embedded-ntp-client-ntp-interleaved-mode-part-2/] In this post, I wrap up my embedded NTP client and use it to measure the difference between my other two NTP servers with hardware timestamps. Goal 1: synchronize the local clock
Previous post: https://blog.dan.drown.org/stm32mp1-ntp-server/ [https://blog.dan.drown.org/stm32mp1-ntp-server/] I figured out my offset problem, which was not a PLL problem like I thought. Connman has a NTP client enabled by default :(The distro I'm using uses connman by default to manage the network interfaces.
Previous post: Debian for STM32MP1 [https://blog.dan.drown.org/debian-for-stm32mp1/] NIC Hardware Timestamps First step: enable hardware timestamps in chrony.conf: chrony configuration for hardware timestampsNext, enable chrony's measurements log, and verify it's using hardware timestamps (H) not kernel timestamps (K): it's using kernel timestampsLooking into why it wasn't
I bought a STM32MP1 dev board [https://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html] because it has a gigabit NIC with 1588 PTP timestamps as well as hardware timers that can timestamp PPS events without interrupt latency and jitter. I am hoping that it will both be better than the
I wanted a simple keyboard with play and pause media keys to make it convenient to control my music. To handle the USB, I used a STM32F103 based "blue pill" board because they're cheap and easy to work with. First I put together a simple design in easyEDA. For the
Hardware transmit timestamps added to NTP client.